The present invention relates generally to field of metal oxide semiconductor field effect transistors (MOSFETs), and has specific application to the fabrication of these devices in the context of an integrated circuit (IC).
Since the invention of the transistor in the late 1940s, tremendous advances have been made in the field of microelectronics. Current technology allows for the cost-effective fabrication of integrated circuits (ICs) with over 100 million componentsxe2x80x94all on a piece of silicon roughly 10 mm on a side. The one billion transistor IC will be commercially available within a few years. The desire for greater functionality and performance at less cost per IC drives several trends.
First, functionality drives IC transistor counts up. Second, the transistors themselves are being reduced in size so as to achieve greater packing density and, very importantly, to improve their performance. As far as performance is concerned, the key parameter for Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFETs, the dominant transistor technology of the day) is the channel length. The channel length (L) is the distance that charge carriers must travel to pass through the device, and a reduction in this length simultaneously implies higher current drives, reduced parasitic resistances and capacitances and improved high-frequency performance. A common figure-of-merit is the power-delay product, and this generalized measure of transistor performance improves as the cube of the inverse of the channel length (1/L3). This explains the tremendous incentive that IC manufacturers have to reduce the channel length as much as manufacturing capabilities will allow.
For digital applications, MOS transistors behave like switches. When xe2x80x98onxe2x80x99, they drive relatively large amounts of current, and when turned xe2x80x98offxe2x80x99 they are characterized by a certain amount of leakage current. As channel lengths are reduced, drive currents increase, which is beneficial for circuit performance as stated above. However, leakage currents increase as well. Leaky transistors contribute to quiescent power dissipation (the power dissipated by an IC when idle) and in extreme cases can affect the transfer of binary information during active operation. Device designers therefore have good reason to keep leakage currents low as channel lengths are reduced.
MOS transistor leakage currents are traditionally controlled by introducing controlled amounts of impurities (dopants) into the channel region of the device, and by tailoring the source/drain lateral and vertical doping distributions. Although these approaches are effective in shoring up the potential barrier internal to the MOS transistor and therefore reducing the leakage current, they can also contribute to degraded drive current and increased parasitic capacitancexe2x80x94the very items that channel length reduction is meant to improve. Furthermore, depending on exactly how in the manufacturing process the channel and tailored source/drain dopants are introduced, the manufacturing cost can be affected significantly. Given traditional MOS transistor design and architecture, there are only limited solutions to the trade-off between drive current, leakage current, parasitic capacitance and resistance, and manufacturing complexity/cost.
The present invention offers a new relationship between these competing requirements, and makes possible MOS devices with characteristics that are not achievable with traditional (impurity doped) MOS architectures. The use of metal for the source and drain and a simple, uniformly implanted channel dopant profile provides for improvements to device characteristics in terms of reduced parasitic capacitance, reduced statistical variations in these characteristics (especially as the channel length is decreased) and reduced manufacturing cost and complexity.
Doping Profiles
Previous generations of MOS transistors have relied on laterally uniform, and vertically non-uniform channel doping profiles to control drain-to-source leakage currents. See Yuan Taur, xe2x80x9cThe Incredible Shrinking Transistorxe2x80x9d, IEEE SPECTRUM, pages 25-29 (www.spectrum.ieee.org, ISSN 0018-9235, July 1999). FIG. 1 illustrates an exemplary long-channel conventional MOS device (100) that comprises an impurity doped source (101), an impurity doped drain (102), a conventional MOS type gate stack (103), and a laterally uniform channel doping profile (104) in the substrate to assist in the control of source-to-drain leakage currents. Devices are electrically isolated from each other via a field oxide (105). Such channel dopant profiles are common in devices with channel lengths down to approximately 200 nanometers (nm).
However, as device channel lengths have been reduced into the 100 nm regime the literature teaches that channel doping profiles that are non-uniform in both the lateral and vertical directions are required. Referencing FIG. 2, the exemplary short-channel MOS device (200) has some elements similar to the long-channel MOS device (100). The structure comprises a conventional impurity doped source (201) and drain (202) as well as a conventional MOS gate stack (203) (width  less than xcx9c100 nm, corresponding to the channel length L). The structure further comprises shallow, impurity doped extensions for the source (208) and drain (209) electrodes which are used in conjunction with drain (206) and source (207) pocket doping as well as conventional channel doping (204) to control source to drain leakage currents. Source and drain electrodes (201) and (202) and their respective extensions (208) and (209) (the combination of all four of which comprise the tailored source/drain doping profile) are all of the same doping polarity (either N-type or P-type) and are of the opposite polarity from the channel (204) and pocket doping elements (206) and (207). Again, a field oxide (205) electrically isolates devices from each other.
In his paper entitled xe2x80x9c25 nm CMOS Design Considerationsxe2x80x9d (1998 IEDM Technical Digest, page 789), Yuan Taur states
xe2x80x9c. . . an optimized, vertically and laterally non-uniform doping profile, called the super-halo, is needed to control the short channel effect.xe2x80x9d
A similar statement has been made in the IEEE Spectrum magazine:
xe2x80x9c. . . in the 100 to 130 nm lithography generation, an optimally tailored profile that is both vertically and laterally non-uniform (Super-Halo) is need to control [short channel effects].xe2x80x9d
See Linda Geppert, xe2x80x9cThe 100-Million Transistor ICxe2x80x9d, IEEE SPECTRUM, pages 23-24 (www.spectrum.ieee.org, ISSN 0018-9235, July 1999).
Furthermore, virtually all the prior art that discusses device design for channel lengths less than 200 nm states or implies that channel doping profiles that are highly non-uniform in both the lateral and vertical directions are required for adequate control of drain-to-source leakage currents. For example, Hargrove in his paper xe2x80x9cHigh-Performance sub 0.08 um CMOS with Dual Gate Oxide and 9.7 ps Inverter Delay (1998 IEDM, page 627) states
xe2x80x9cIn order to achieve optimal device performance . . . strong halos coupled with shallow junctions are required.xe2x80x9d
The prior art is virtually unanimous in its statement that laterally and vertically non-uniform doping profiles, in the form of laterally non-uniform channel dopants and shallow source/drain extensions, are required for adequate control of short channel effects.
Pocket/Halo Implants
Laterally non-uniform channel doping profiles are almost exclusively introduced after the gate electrode has been defined and is in place. With the gate serving as an implant mask, dopants of the same type as those already in the substrate are introduced into the channel regions adjacent to the gate electrode""s edges via ion-implantation. As mentioned previously, these are often referred to as xe2x80x9cpocketxe2x80x9d or xe2x80x9chaloxe2x80x9d implants. See Yuan Taur, xe2x80x9cThe Incredible Shrinking Transistorxe2x80x9d, IEEE SPECTRUM, page 28 (www.spectrum.ieee.org, ISSN 0018-9235, July 1999).
While effective at reinforcing the electrostatic potential barrier between the source and drain (and therefore reducing leakage currents), Halo/Pocket implants along with shallow source/drain extensions (the tailored source/drain doping profiles mentioned previously) add complexity to the manufacturing process. At least two additional lithography steps, as well as the associated cleans, implants, metrology, etc. are required to implement these process steps. As lithography is one of the most (if not the most) expensive process modules in the production process, this is a significant increase in manufacturing cost. Halo and Pocket implants as well as shallow source/drain extensions can also add parasitic capacitance and a random statistical variation to device electrical characteristics.
Channel doping profiles for short channel Schottky MOS devices have received only very limited attention in the prior art. J. R. Tucker discusses simulations done on very short channel SBMOS devices and only mentions in passing that
xe2x80x9c. . . some doping of the semiconductor channel region will be required in order to suppress (leakage) currents . . . xe2x80x9d
See J. R. Tucker, C. Wang, J. W. Lyding, T. C. Shen, G. C. Abeln, xe2x80x9cNanometer Scale MOSFETs and STM Patterning on Si,xe2x80x9d SSDM 1994, pages 322-324; J. R. Tucker, C. Wang, P. S. Carney, xe2x80x9cSilicon Field-Effect Transistor Based on Quantum Tunneling,xe2x80x9d Applied Physics Letters, Aug. 1, 1994, Vol. 65, No. 5, pages 618-620. It is significant to note that Tucker does not discuss in what manner one might go about introducing channel doping to suppress source-to-drain leakage currents.
Q. T. Zhao is the next author to explicitly address the issue of channel doping to control leakage currents. His approach (uniform doping of the substrate to quite high levels (1017/cm3)) is well known to be non-optimal for short channel devices. Although he is successful in reducing leakage currents, he does so at the expense of increased source/drain-to-substrate capacitance. See Q. T. Zhao, F. Klinkhammer, M. Dolle, L. Kappius, S. Mantl, xe2x80x9cNanometer patterning of epitaxial CoSi2/Si(100) for ultrashort channel Schottky barrier metal-oxide-semiconductor field effect transistors,xe2x80x9d APPLIED PHYSICS LETTERS, Vol. 74 No. 3, January 18, 1999, page 454.
W. Saitoh reports on a device built on SOI substrates but does not discuss substrate doping in this context. See W. Saitoh, S. Yamagami, A. ltoh, M. Asada, xe2x80x9c35 nm metal gate SOI-P-MOSFETs with PtSi Schottky source/drain,xe2x80x9d Device Research Conference, Jun. 28-30, 1999, Santa Barbara, Calif., Paper II.A.6, page 30.
C. Wang mentions the use of xe2x80x9ca layer of fully-depleted dopants beneath the active regionxe2x80x9d and xe2x80x9cpreimplanting a thin subsurface layer of fully depleted dopantsxe2x80x9d to control leakage currents, but does not describe the lateral uniformity or lack thereof of the doping profile, or how one might go about producing the xe2x80x9clayerxe2x80x9d. See C. Wang, John P. Snyder, J. R. Tucker, xe2x80x9cSub-40 nm PtSi Schottky source/drain metal-oxide-semiconductor field-effect-transistors,xe2x80x9d APPLIED PHYSICS LETTERS, Vol. 74 No. 8, Feb. 22, 1999, pages 1174; C. Wang, John P. Snyder, J. R. Tucker, xe2x80x9cSub-50 nm PtSi Schottky source/drain P-MOSFETs,xe2x80x9d Annual Device Research Conference Digest 1998, pages 72-73.
Summary
Given the literature on substrate doping profiles for conventional short channel MOS transistors and the scant work on channel doping profiles for short channel Schottky MOS devices, the proposed invention offers a novel and non-obvious MOSFET device and fabrication approach with many advantages over the current state-of-the-art.
Accordingly, the objects of the present invention are (among others) to circumvent the deficiencies in the prior art and affect one or more of the following objectives:
1. Provide a system and method to permit MOSFETs to be fabricated with short channel lengths with less cost, higher performance and better tolerances than current fabrication technologies.
2. Reduce parasitic bipolar operation in integrated MOSFETs, thus reducing the potential for latchup and other anomalous behavior.
3. Provide for MOSFET devices that have in some circumstances a higher degree of radiation hardness.
While these objectives should not be understood to limit the teachings of the present invention, in general these objectives are achieved by the disclosed invention that is discussed in the following sections.
Overview
Referencing FIG. 3, an exemplary embodiment of the present invention (300) consists simply of a conventional MOS gate stack (303) (gate electrode on silicon dioxide on a silicon substrate), metal source (301) and/or drain (302) electrodes, and channel dopants (304) that vary significantly in the vertical direction but not in the lateral direction. A field oxide (305) electrically isolates devices from each other.
The Schottky (or Schottky-like) barriers (307, 308) that exist along the interface of the corresponding metal source/drain (301, 302) and the silicon substrate (306) act as an inherent pocket or halo implant and does so without added parasitic capacitance. It also eliminates the need for shallow source/drain extensions as the metal source/drain is by its nature shallow and highly conductive. Significant reductions in manufacturing complexity are therefore achieved by simultaneous elimination of the halo/pocket implants and the source/drain extensions. These are also major advantages over conventionally-architected-channel MOS devices.
Due to the atomically abrupt nature of the Schottky barrier and the very consistent and repeatable magnitude of this barrier, two sources of statistical variation which are endemic to conventional MOS devices are virtually eliminated. The random statistical nature of dopant introduction via ion-implantation in conventional devices produces significant variations in the position and magnitude of implanted dopants. This is true for both the halo/pocket and source/drain dopants. The result is a certain amount of random variation in device parameters such as channel length (L), drive current, and leakage current. These variations make circuit design more difficult and contribute to manufacturing cost via yield loss due to ICs that do not meet performance specifications. The problem becomes more severe as channel lengths are reduced due to the smaller effective volume of silicon per device, and therefore less averaging to smooth away statistical variations.
Because the metal source/drain (which replaces the conventional impurity doped source/drain) has a natural, very consistent and atomically abrupt Scotty barrier (307, 308) with the silicon substrate (306) whose position and magnitude are independent of channel length, and because this barrier essentially plays the role of the halo/pocket implant (making these implants unnecessary), statistical variations due to random placement of atoms during the source/drain and halo/pocket implants are essentially eliminated. This fact remains true and even becomes more true as the channel length is reduced.
Another benefit of the metal source/drain MOS architecture is the unconditional elimination of the parasitic bipolar gain. The parasitic bipolar gain is a direct result of using opposite doping types for the source/drain and substrate regions, and can result in latch-up and other deleterious effects. When the source/drain electrodes are constructed of metal, this parasitic gain is eliminated. This makes the metal source/drain architecture ideal for (among other things) high-radiation environments.
General Advantages
The present invention typically provides the following benefits as compared to the prior art:
1. Reduction in manufacturing complexity. Pocket/Halo implants and shallow source/drain extensions are not needed.
2. Reduction in capacitance due to absence of pocket/halo implants.
3. Reduction in random/statistical variations of device electrical characteristics due to absence of pocket/halo implants and course/drain extensions, and the use of metal for the source and drain.
4. Unconditional elimination of the parasitic bipolar gain and associated latchup.
5. Increased radiation hardness as compared to conventional MOS structures.
The above list of advantages should not be interpreted as to limit the scope of the present invention. However, one skilled in the art will recognize a plethora of application opportunities for the present invention teachings given the above-mentioned list of general advantages that are potentially available.